`timescale 1ns / 1ps

module change_xyz (
    input   wire    [9:0]   x_in    , // 抓取位置x
    input   wire    [9:0]   y_in    , // 抓取位置y

    output  wire    [7:0]   x_o     , // 抓取位置x
    output  wire    [7:0]   y_o       // 抓取位置y
);

wire    [9:0]  y_10_b;
wire    [9:0]  x_10_b;

assign x_o  = 8'd105 - x_10_b[7:0];
assign y_o  = 8'd228 - y_10_b[7:0];

mult1	mult1_1_inst (
	.dataa  ( y_in       ),
	.datab  ( 14'd4357   ),
	.result ( y_10_b     )
);

mult1	mult1_2_inst (
	.dataa  ( x_in       ),
	.datab  ( 14'd3397   ),
	.result ( x_10_b     )
);
/*
85 + y_in * 0.2083 85 + 600 *  = 85 + 125 = 210
483
0 -> 96
1024 -> -96
96 - 192 / 997 * 997 = -96
96 - 192 / 997 * 30 = 96

926 470

18
	125
		16.4

9.3
  192
     11
96 - 1024 * 192/1024
*/

endmodule